The University of Southampton
University of Southampton Institutional Repository

Recent developments in deca-nanometer vertical MOSFETs

Recent developments in deca-nanometer vertical MOSFETs
Recent developments in deca-nanometer vertical MOSFETs
We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.
0167-9317
230-235
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Donaghy, S.
ed32d106-dd25-466d-a4e0-bde4f4c1f09d
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Kunz, V.D.
c4efd0d1-d850-414d-9c33-12029ac3e060
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Donaghy, S.
ed32d106-dd25-466d-a4e0-bde4f4c1f09d
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Kunz, V.D.
c4efd0d1-d850-414d-9c33-12029ac3e060
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Hall, S., Donaghy, S., Buiu, O., Gili, E., Uchino, T., Kunz, V.D., de Groot, C.H. and Ashburn, P. (2004) Recent developments in deca-nanometer vertical MOSFETs. Microelectronic Engineering, 72, 230-235. (doi:10.1016/j.mee.2003.12.042).

Record type: Article

Abstract

We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.

Text
Microelectronics_engineering.pdf - Other
Download (409kB)

More information

Published date: 2004
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260148
URI: http://eprints.soton.ac.uk/id/eprint/260148
ISSN: 0167-9317
PURE UUID: fdb1b92a-2339-4743-9b04-7893f348cad4
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 25 Nov 2004
Last modified: 17 Dec 2019 01:51

Export record

Altmetrics

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×