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Recent developments in deca-nanometer vertical MOSFETs

Hall, S., Donaghy, S., Buiu, O., Gili, E., Uchino, T., Kunz, V.D., de Groot, C.H. and Ashburn, P. (2004) Recent developments in deca-nanometer vertical MOSFETs Microelectronic Engineering, 72, pp. 230-235. (doi:10.1016/j.mee.2003.12.042).

Record type: Article

Abstract

We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.

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Published date: 2004
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260148
URI: http://eprints.soton.ac.uk/id/eprint/260148
ISSN: 0167-9317
PURE UUID: fdb1b92a-2339-4743-9b04-7893f348cad4
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 25 Nov 2004
Last modified: 18 Jul 2017 09:15

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Contributors

Author: S. Hall
Author: S. Donaghy
Author: O. Buiu
Author: E. Gili
Author: T. Uchino
Author: V.D. Kunz
Author: C.H. de Groot ORCID iD
Author: P. Ashburn

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