Recent developments in deca-nanometer vertical MOSFETs

Hall, S., Donaghy, S., Buiu, O., Gili, E., Uchino, T., Kunz, V.D., de Groot, C.H. and Ashburn, P. (2004) Recent developments in deca-nanometer vertical MOSFETs Microelectronic Engineering, 72, pp. 230-235. (doi:10.1016/j.mee.2003.12.042).


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We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.

Item Type: Article
Digital Object Identifier (DOI): doi:10.1016/j.mee.2003.12.042
ISSNs: 0167-9317 (print)
Organisations: Nanoelectronics and Nanotechnology
ePrint ID: 260148
Date :
Date Event
Date Deposited: 25 Nov 2004
Last Modified: 17 Apr 2017 22:17
Further Information:Google Scholar

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