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Realization and characterization of vertical MOSFETs with reduced parasitic capacitance

Realization and characterization of vertical MOSFETs with reduced parasitic capacitance
Realization and characterization of vertical MOSFETs with reduced parasitic capacitance
81-82
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Kunz, V. D.
2e608ea3-6eb5-44c4-a123-865f92d5186a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Gili, E.
6e227036-b8f4-4364-a0ce-28c3899294b8
Kunz, V. D.
2e608ea3-6eb5-44c4-a123-865f92d5186a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Gili, E., Kunz, V. D., Uchino, T., de Groot, C.H. and Ashburn, P. (2003) Realization and characterization of vertical MOSFETs with reduced parasitic capacitance. PREP, Exeter (), United Kingdom. 13 - 15 Apr 2003. pp. 81-82 .

Record type: Conference or Workshop Item (Other)
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PREP2003-EnricoGili.pdf - Other
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More information

Published date: 2003
Additional Information: Event Dates: 14-16 April
Venue - Dates: PREP, Exeter (), United Kingdom, 2003-04-13 - 2003-04-15
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260153
URI: http://eprints.soton.ac.uk/id/eprint/260153
PURE UUID: 9e74522e-866f-4f29-aaf5-776c12938d62
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 26 Nov 2004
Last modified: 30 Jan 2020 01:31

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Contributors

Author: E. Gili
Author: V. D. Kunz
Author: T. Uchino
Author: C.H. de Groot ORCID iD
Author: P. Ashburn

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