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CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance.

CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance.
CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance.
221-224
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Gili, E
68792585-bbb1-4358-a8ca-c1b4b012cb4e
Uchino, T
5c7413a3-c3f6-41ee-8a74-1614054f63e4
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Kunz, V D
2974a8ef-fe2d-42f6-a7a8-7de682c5752a
de Groot, C H
92cd2e02-fcc4-43da-8816-c86f966be90c
Gili, E
68792585-bbb1-4358-a8ca-c1b4b012cb4e
Uchino, T
5c7413a3-c3f6-41ee-8a74-1614054f63e4
Hall, S
f4a3297d-bb12-404d-9a02-f082ba4cbfb0
Ashburn, P
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Kunz, V D, de Groot, C H, Gili, E, Uchino, T, Hall, S and Ashburn, P (2004) CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance. 34th European Solid State Device Research Conference (ESSDERC), Belgium. 21 - 23 Sep 2004. pp. 221-224 .

Record type: Conference or Workshop Item (Other)
Text
ESSDERC2004VDKunz.pdf - Other
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More information

Published date: September 2004
Additional Information: Event Dates: 21-23 September
Venue - Dates: 34th European Solid State Device Research Conference (ESSDERC), Belgium, 2004-09-21 - 2004-09-23
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260762
URI: http://eprints.soton.ac.uk/id/eprint/260762
PURE UUID: b6c615f0-ef73-4670-9047-44679a1dd497
ORCID for C H de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 14 Apr 2005
Last modified: 29 Oct 2019 01:55

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