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CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance.

Record type: Conference or Workshop Item (Other)
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Citation

Kunz, V D, de Groot, C H, Gili, E, Uchino, T, Hall, S and Ashburn, P (2004) CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance. At 34th European Solid State Device Research Conference (ESSDERC), Belgium. 21 - 23 Sep 2004. , pp. 221-224.

More information

Published date: September 2004
Additional Information: Event Dates: 21-23 September
Venue - Dates: 34th European Solid State Device Research Conference (ESSDERC), Belgium, 2004-09-21 - 2004-09-23
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 260762
URI: http://eprints.soton.ac.uk/id/eprint/260762
PURE UUID: b6c615f0-ef73-4670-9047-44679a1dd497
ORCID for C H de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 14 Apr 2005
Last modified: 18 Jul 2017 09:09

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Contributors

Author: V D Kunz
Author: C H de Groot ORCID iD
Author: E Gili
Author: T Uchino
Author: S Hall
Author: P Ashburn

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