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Multi-FPGA Synthesis with Asynchronous Communication Subsystems

Multi-FPGA Synthesis with Asynchronous Communication Subsystems
Multi-FPGA Synthesis with Asynchronous Communication Subsystems
With the ever-increasing complexity of digital designs, design abstraction has increased from schematic to language-based, and is migrating towards abstract behavioural specifications. Partitioning of the circuit or system into a collection of smaller, manageable components has become a central and critical design task. Asynchronous techniques of data synchronisation between partitioned designs, often in different clock domains, are well-researched areas in low power, and system on chip designs. In this paper, we present a high-level synthesis system that synthesises and generates structural outputs of a multi-FPGA system automatically without any modification of the source HDL code. The targeting of multiple prototyping boards trades off performance for improvement in prototyping time and cost. Optimised asynchronous communications channels with communications cells are inserted automatically to the multi-FPGA implementation during synthesis, synchronising inter-FPGA data packets transferred asynchronously between FPGAs in different clock domains.
High-level synthesis, multi-FPGA systems
Yee, Tack Boon
f9d970a9-5346-4fd8-b5bb-aa502aa14340
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Brown, Andrew D
5c19e523-65ec-499b-9e7c-91522017d7e0
Yee, Tack Boon
f9d970a9-5346-4fd8-b5bb-aa502aa14340
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Brown, Andrew D
5c19e523-65ec-499b-9e7c-91522017d7e0

Yee, Tack Boon, Zwolinski, Mark and Brown, Andrew D (2005) Multi-FPGA Synthesis with Asynchronous Communication Subsystems At IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2005).

Record type: Conference or Workshop Item (Paper)

Abstract

With the ever-increasing complexity of digital designs, design abstraction has increased from schematic to language-based, and is migrating towards abstract behavioural specifications. Partitioning of the circuit or system into a collection of smaller, manageable components has become a central and critical design task. Asynchronous techniques of data synchronisation between partitioned designs, often in different clock domains, are well-researched areas in low power, and system on chip designs. In this paper, we present a high-level synthesis system that synthesises and generates structural outputs of a multi-FPGA system automatically without any modification of the source HDL code. The targeting of multiple prototyping boards trades off performance for improvement in prototyping time and cost. Optimised asynchronous communications channels with communications cells are inserted automatically to the multi-FPGA implementation during synthesis, synchronising inter-FPGA data packets transferred asynchronously between FPGAs in different clock domains.

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More information

Published date: 2005
Venue - Dates: IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2005), 2005-01-01
Keywords: High-level synthesis, multi-FPGA systems
Organisations: EEE

Identifiers

Local EPrints ID: 261305
URI: http://eprints.soton.ac.uk/id/eprint/261305
PURE UUID: 53b2d86f-4f2c-488d-a4bd-31cfcf1283fb
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 07 Oct 2005
Last modified: 18 Jul 2017 09:03

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Contributors

Author: Tack Boon Yee
Author: Mark Zwolinski ORCID iD
Author: Andrew D Brown

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