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Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs

Record type: Article

We investigate the validity of the assumption of neglecting carrier tunneling effects on self-consistent electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. Comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high- gate dielectrics.

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Citation

Hakim, MMA and Haque, A (2002) Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs IEEE Transaction on Electron Devices, 49, (9), pp. 1669-1671.

More information

Published date: 2002
Organisations: Nanoelectronics and Nanotechnology

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Local EPrints ID: 262447
URI: http://eprints.soton.ac.uk/id/eprint/262447
PURE UUID: 2aaf381b-efea-4eaa-b5d5-abc6bf9fdd1e

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Date deposited: 02 May 2006
Last modified: 18 Jul 2017 08:51

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Contributors

Author: MMA Hakim
Author: A Haque

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