Collins, Matthew, Al-Hashimi, Bashir and Wilson, Peter (2006) On-chip timing measurement architecture with femtosecond resolution. Electronics Letters, 42 (9), 528-530.
Record type:
Article
Abstract
A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185µm) in a 0.12µm CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.
More information
Published date: April 2006
Organisations:
Electronic & Software Systems, EEE
Identifiers
Local EPrints ID: 262543
URI: http://eprints.soton.ac.uk/id/eprint/262543
ISSN: 0013-5194
PURE UUID: d2f24d54-f86e-47cf-8016-6f1b809c2282
Catalogue record
Date deposited: 11 May 2006
Last modified: 14 Mar 2024 07:13
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Contributors
Author:
Matthew Collins
Author:
Bashir Al-Hashimi
Author:
Peter Wilson
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