Area Word-Length Trade off in DSP Algorithm Implementation and Optimization


Ahmadi, Arash and Zwolinski, Mark (2005) Area Word-Length Trade off in DSP Algorithm Implementation and Optimization At IEE/EURASIP Conference on DSPenabledRadio, United Kingdom. 19 - 20 Sep 2005. , 16/1-16/6.

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Description/Abstract

This paper proposes a frame work for High Level Synthesis of DSP algorithms with emphasis on differences between DSP systems and other digital systems. Accordingly a multiple word length has been used to optimize the system digital noise and area trade off. Based on a proposed architecture, required cost function, synthesiser and optimizer and intermediate data bases have been introduced and implemented. Optimization has been done by an optimizer based on Genetic Algorithm

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: 19-20 Sept. 2005
Venue - Dates: IEE/EURASIP Conference on DSPenabledRadio, United Kingdom, 2005-09-19 - 2005-09-20
Organisations: EEE
ePrint ID: 262744
Date :
Date Event
2005Published
Date Deposited: 18 Sep 2006
Last Modified: 17 Apr 2017 21:37
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/262744

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