Thermal-Aware Soc Test Scheduling with Test Set Partitioning and Interleaving
Thermal-Aware Soc Test Scheduling with Test Set Partitioning and Interleaving
Low-power test, VLSI test
Zhiyuan, He
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Peng, Zepo
0938f078-7c30-43e0-9bd2-a2bc70d6941b
Eles, Petru
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Rosinger, Paul
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Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
January 2007
Zhiyuan, He
4cb7660a-f1ce-459f-9679-1b6f3f14375e
Peng, Zepo
0938f078-7c30-43e0-9bd2-a2bc70d6941b
Eles, Petru
ff663918-4c91-4774-a196-06d87393323f
Rosinger, Paul
b4dae52c-aeb6-4e07-8a63-d6deaae76ef2
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhiyuan, He, Peng, Zepo, Eles, Petru, Rosinger, Paul and Al-Hashimi, Bashir M.
(2007)
Thermal-Aware Soc Test Scheduling with Test Set Partitioning and Interleaving.
JETTA.
Text
jetta_dft1.pdf
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More information
Published date: January 2007
Keywords:
Low-power test, VLSI test
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 263314
URI: http://eprints.soton.ac.uk/id/eprint/263314
PURE UUID: 589afa6a-fe96-46bf-a9c6-17f9d8588cae
Catalogue record
Date deposited: 14 Jan 2007
Last modified: 14 Mar 2024 07:29
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Contributors
Author:
He Zhiyuan
Author:
Zepo Peng
Author:
Petru Eles
Author:
Paul Rosinger
Author:
Bashir M. Al-Hashimi
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