Behavioural synthesis of an adaptive Viterbi decoder
Behavioural synthesis of an adaptive Viterbi decoder
The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Reeve, JS
dd909010-7d44-44ea-83fe-a09e4d492618
2005
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Reeve, JS
dd909010-7d44-44ea-83fe-a09e4d492618
Zwolinski, M and Reeve, JS
(2005)
Behavioural synthesis of an adaptive Viterbi decoder.
DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, Southampton, United Kingdom.
19 - 20 Sep 2004.
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Abstract
The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.
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DSPeRBehavioural.pdf
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Published date: 2005
Additional Information:
Event Dates: SEP 19-20, 2004
Venue - Dates:
DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, Southampton, United Kingdom, 2004-09-19 - 2004-09-20
Organisations:
EEE
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Local EPrints ID: 263415
URI: http://eprints.soton.ac.uk/id/eprint/263415
PURE UUID: d12c4850-1f17-490c-815c-190e5206326c
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Date deposited: 12 Feb 2007
Last modified: 15 Mar 2024 02:39
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Author:
M Zwolinski
Author:
JS Reeve
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