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Behavioural synthesis of an adaptive Viterbi decoder

Record type: Conference or Workshop Item (Paper)

The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

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Citation

Zwolinski, M and Reeve, JS (2005) Behavioural synthesis of an adaptive Viterbi decoder At DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, United Kingdom. 19 - 20 Sep 2004.

More information

Published date: 2005
Additional Information: Event Dates: SEP 19-20, 2004
Venue - Dates: DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, United Kingdom, 2004-09-19 - 2004-09-20
Organisations: EEE

Identifiers

Local EPrints ID: 263415
URI: http://eprints.soton.ac.uk/id/eprint/263415
PURE UUID: d12c4850-1f17-490c-815c-190e5206326c
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 12 Feb 2007
Last modified: 18 Jul 2017 07:45

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Contributors

Author: M Zwolinski ORCID iD
Author: JS Reeve

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