Modified virtually scaling free adaptive CORDIC rotator algorithm and architecture

Maharatna, Koushik, Banerjee, Swapna, Grass, Eckhard, Krstic, Milos and Troya, Alfonso (2005) Modified virtually scaling free adaptive CORDIC rotator algorithm and architecture IEEE Transactions on Circuits and Ssystems for Video Technology, 15, (11), pp. 1463-1474.


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In this article we proposed a novel CoOrdinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that depending on the input angle the scale factor can assume only two values viz., 1 and 1/?2 and it is independent of the number of executed iteration, nature of iteration and wordlength. In this algorithm, compared to the conventional CORDIC a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm2 and its power dissipation is 7 mW in IHP in-house 0.25 ?m BiCMOS technology. To our knowledge, this is the smallest pipelined CORDIC rotator reported so far.

Item Type: Article
Additional Information: nonValidatingUrl:L:\soton\paper_related\published\cordic_csvt.pdf
Keywords: CORDIC, Vector rotation, DSP, VLSI, Scaling free CORDIC
Organisations: Electronic & Software Systems
ePrint ID: 263498
Date :
Date Event
November 2005Published
Date Deposited: 19 Feb 2007
Last Modified: 17 Apr 2017 19:52
Further Information:Google Scholar

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