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New virtually scaling free adaptive CORDIC rotator

New virtually scaling free adaptive CORDIC rotator
New virtually scaling free adaptive CORDIC rotator
In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2.
448-456
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Troya, Alfonso
ee29f224-5c44-4219-a287-c6f21b1438a7
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb
Grass, Eckhard
8936f993-c0cc-4507-af71-07e97d3cf9d1

Maharatna, Koushik, Troya, Alfonso, Banerjee, Swapna and Grass, Eckhard (2004) New virtually scaling free adaptive CORDIC rotator. IEE Proceedings on Computers and Digital Techniques, 151 (6), 448-456.

Record type: Article

Abstract

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2.

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More information

Published date: November 2004
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263504
URI: https://eprints.soton.ac.uk/id/eprint/263504
PURE UUID: 623a2fb0-26fb-493a-b330-7e5185a3500d

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Date deposited: 19 Feb 2007
Last modified: 18 Jul 2017 07:45

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Contributors

Author: Alfonso Troya
Author: Swapna Banerjee
Author: Eckhard Grass

University divisions

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