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A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST

A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST
A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST
A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for Wafer Scale Integration (WSI). CORDIC is designed using Transmission Gate Logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications.
Keyword : VLSI, CORDIC, Wavefront array, DFT, DHT, DCT, DST.
1813-1822
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Dhar, Anindya Sunder
b47b200f-a8f2-49bd-89e3-9b4988b22a03
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Dhar, Anindya Sunder
b47b200f-a8f2-49bd-89e3-9b4988b22a03
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb

Maharatna, Koushik, Dhar, Anindya Sunder and Banerjee, Swapna (2001) A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST. Journal of Signal Processing, 81, 1813-1822.

Record type: Article

Abstract

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for Wafer Scale Integration (WSI). CORDIC is designed using Transmission Gate Logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications.

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Published date: 2001
Keywords: Keyword : VLSI, CORDIC, Wavefront array, DFT, DHT, DCT, DST.
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263517
URI: https://eprints.soton.ac.uk/id/eprint/263517
PURE UUID: a67fe0c6-ee3c-4140-9c4e-ae15b91f7908

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Date deposited: 19 Feb 2007
Last modified: 19 Jul 2019 22:29

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Contributors

Author: Anindya Sunder Dhar
Author: Swapna Banerjee

University divisions

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