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A VLSI Array Architecture for Hough Transform

A VLSI Array Architecture for Hough Transform
A VLSI Array Architecture for Hough Transform
Hough transform, CORDIC, low power, image processing, multiplierless array architecture
0031-3203
1503-1512
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Banerjee, Swapna
0e62324f-d76b-4242-9044-380e4a865adb

Maharatna, Koushik and Banerjee, Swapna (2001) A VLSI Array Architecture for Hough Transform. Pattern Recognition, 34, 1503-1512.

Record type: Article
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Published date: 2001
Keywords: Hough transform, CORDIC, low power, image processing, multiplierless array architecture
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263519
URI: https://eprints.soton.ac.uk/id/eprint/263519
ISSN: 0031-3203
PURE UUID: 5a60a11e-99c7-4e83-a3fe-aa486862a5d6

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Date deposited: 19 Feb 2007
Last modified: 19 Jul 2019 22:29

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