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Impact of strain on the design of low-power high-speed circuits

Impact of strain on the design of low-power high-speed circuits
Impact of strain on the design of low-power high-speed circuits
In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has been given on the evaluation of noise characteristics and low-power performance along with the delay characteristics under different channel straining conditions. An inverter circuit has been used for performance evaluation through simulation where the device simulator is calibrated with experimental device data. The result shows a great promise for s-Si technology in digital applications which require high throughput and low power.
Low power, Strained Silicon
Ramkrishnan, Hiran
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Maharatna, Koushik
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Chattopadhyay, Sanatan
027d649f-07a2-41ac-8902-a71f74ec75cf
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
O'Neill, Anthony
20c8b9f6-211a-4657-8f35-c9463ae6b48e
Ramkrishnan, Hiran
efb6511b-a42a-472d-b042-05887155f91d
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Chattopadhyay, Sanatan
027d649f-07a2-41ac-8902-a71f74ec75cf
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
O'Neill, Anthony
20c8b9f6-211a-4657-8f35-c9463ae6b48e

Ramkrishnan, Hiran, Maharatna, Koushik, Chattopadhyay, Sanatan, Yakovlev, Alex and O'Neill, Anthony (2007) Impact of strain on the design of low-power high-speed circuits. IEEE International Symposium on Circuits and Systems.

Record type: Conference or Workshop Item (Paper)

Abstract

In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has been given on the evaluation of noise characteristics and low-power performance along with the delay characteristics under different channel straining conditions. An inverter circuit has been used for performance evaluation through simulation where the device simulator is calibrated with experimental device data. The result shows a great promise for s-Si technology in digital applications which require high throughput and low power.

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RamakrishnanH_ISCAS2007.pdf - Other
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More information

Published date: 2007
Venue - Dates: IEEE International Symposium on Circuits and Systems, 2007-01-01
Keywords: Low power, Strained Silicon
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 263529
URI: https://eprints.soton.ac.uk/id/eprint/263529
PURE UUID: 4dd6138d-175a-4389-8ae0-1027f739a8ce

Catalogue record

Date deposited: 19 Feb 2007
Last modified: 19 Jul 2019 22:28

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Contributors

Author: Hiran Ramkrishnan
Author: Sanatan Chattopadhyay
Author: Alex Yakovlev
Author: Anthony O'Neill

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