Exploration of potential of strained-Si CMOS for ultra low-power circuit design
Exploration of potential of strained-Si CMOS for ultra low-power circuit design
Low power, strained silicon
Ramakrishnan, Hiran
6ea93f69-5ef1-4b24-b8a9-46aab1c52f1f
Chattopadhyay, Sanatan
027d649f-07a2-41ac-8902-a71f74ec75cf
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Shedable, S
cfd70402-0b84-447c-9584-caa109eeafaf
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
2007
Ramakrishnan, Hiran
6ea93f69-5ef1-4b24-b8a9-46aab1c52f1f
Chattopadhyay, Sanatan
027d649f-07a2-41ac-8902-a71f74ec75cf
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Shedable, S
cfd70402-0b84-447c-9584-caa109eeafaf
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Ramakrishnan, Hiran, Chattopadhyay, Sanatan, Maharatna, Koushik, Shedable, S and Yakovlev, Alex
(2007)
Exploration of potential of strained-Si CMOS for ultra low-power circuit design.
8th International Conference on Ultimate Integration on Silicon, Lueven.
Record type:
Conference or Workshop Item
(Paper)
Text
ULIS_FINAL.pdf
- Other
More information
Published date: 2007
Venue - Dates:
8th International Conference on Ultimate Integration on Silicon, Lueven, 2007-01-01
Keywords:
Low power, strained silicon
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 263530
URI: http://eprints.soton.ac.uk/id/eprint/263530
PURE UUID: a8d0e453-67ab-4863-94e7-fd87498cf816
Catalogue record
Date deposited: 19 Feb 2007
Last modified: 14 Mar 2024 07:34
Export record
Contributors
Author:
Hiran Ramakrishnan
Author:
Sanatan Chattopadhyay
Author:
Koushik Maharatna
Author:
S Shedable
Author:
Alex Yakovlev
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics