Ali, Haider and Al-Hashimi, Bashir M. (2007) Architecture level power-performance trade-offs for pipelined design. IEEE Symposium on Circuits and Systems (ISCAS 07), , New Orleans, United States. 27 - 30 May 2007.
Record type:
Conference or Workshop Item
(Paper)
More information
Published date: 2007
Additional Information:
Event Dates: 27-30 May 2007
Venue - Dates:
IEEE Symposium on Circuits and Systems (ISCAS 07), , New Orleans, United States, 2007-05-27 - 2007-05-30
Keywords:
Low-power design, pipelined designs, floating point adders, power analysis
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 263700
URI: http://eprints.soton.ac.uk/id/eprint/263700
PURE UUID: 0f670d56-dfdd-4ff7-b3d0-bf9f421084c3
Catalogue record
Date deposited: 15 Mar 2007
Last modified: 14 Mar 2024 07:37
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Contributors
Author:
Haider Ali
Author:
Bashir M. Al-Hashimi
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