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Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cell

Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cell
Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cell
0013-5194
848-850
Nakazato, K.
b12e41d3-3527-48ed-9ecd-b38f774ba838
Itoh, K.
4ecd900d-dc64-4bb9-aeb6-08b18589563e
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Ahmed, H.
f9dabf57-dea0-4cf9-b989-c812b5eedeaf
Nakazato, K.
b12e41d3-3527-48ed-9ecd-b38f774ba838
Itoh, K.
4ecd900d-dc64-4bb9-aeb6-08b18589563e
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Ahmed, H.
f9dabf57-dea0-4cf9-b989-c812b5eedeaf

Nakazato, K., Itoh, K., Mizuta, Hiroshi and Ahmed, H. (1999) Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cell. Electronics Letters, 35, 848-850.

Record type: Article
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More information

Published date: 1999
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 266226
URI: http://eprints.soton.ac.uk/id/eprint/266226
ISSN: 0013-5194
PURE UUID: a6ceb665-b8e2-4ba6-8d87-ca58219ea7c8

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Date deposited: 22 Jul 2008 09:45
Last modified: 14 Mar 2024 08:23

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Contributors

Author: K. Nakazato
Author: K. Itoh
Author: Hiroshi Mizuta
Author: H. Ahmed

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