Design optimization of NEMS switches for single-electron logic applications
Design optimization of NEMS switches for single-electron logic applications
P1-32
Pruvost, B.
c79e286c-c376-4f31-af2d-b592c9b186a0
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, S.
4a88f225-39f6-4c89-a9da-8c35fbfe6fde
June 2008
Pruvost, B.
c79e286c-c376-4f31-af2d-b592c9b186a0
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, S.
4a88f225-39f6-4c89-a9da-8c35fbfe6fde
Pruvost, B., Mizuta, Hiroshi and Oda, S.
(2008)
Design optimization of NEMS switches for single-electron logic applications.
IEEE Silicon Nanoelectronics Workshop, Honolulu.
.
Record type:
Conference or Workshop Item
(Poster)
Text
cpaper_146.pdf
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More information
Published date: June 2008
Additional Information:
Event Dates: June 2008
Venue - Dates:
IEEE Silicon Nanoelectronics Workshop, Honolulu, 2008-06-01
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 266270
URI: http://eprints.soton.ac.uk/id/eprint/266270
PURE UUID: 5e388275-aba4-4053-b14d-a1eea1123003
Catalogue record
Date deposited: 23 Jul 2008 09:12
Last modified: 14 Mar 2024 08:25
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Contributors
Author:
B. Pruvost
Author:
Hiroshi Mizuta
Author:
S. Oda
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