Effects of oxidation and annealing temperature on grain boundary properties in polycrystalline silicon probed using nanometer-scale point-contact devices

Abstract

Carrier transport in polycrystalline silicon (poly-Si) is affected significantly by
electronic properties of grain boundaries (GBs). As future nanometre-scale devices, such as single-electron transistors (SETs), will have only a few GBs in the active region, the control and characterization of individual GBs will be vital to obtain reliable and reproducible device operation. We have characterized individual GBs in poly-Si using nanometer-scale devices.^[1,2]
In this work, we focus on the effects of oxidation and annealing temperature on the electrical characteristics of GBs. We have fabricated 30-nm-wide point-contact devices in a 50-nm-thick highly-doped n-type poly-Si film. The channel length was varied from 20 nm to 80 nm. These devices were subjected to oxidation in dry O₂ gas at 650^oC -1000^oC for 1 hr. Some devices were followed by annealing in Ar ambient at 1000^oC for15min after the oxidation. We have observed that oxidation at 650^oC - 750^oC oxidises the grain boundaries selectively, and that subsequent annealing increases the associated potential barrier height and tunnel resistance. These are explained by structural changes in the Si-O network at the grain boundaries and the competition between surface oxygen diffusion and oxidation from the GBs into the crystalline grains.

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