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Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture

Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture
Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80mV/decade and DIBL of 30-35mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.
Hakim, M.M.A.
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Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
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Tan, L.
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Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
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Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc

Hakim, M.M.A., Uchino, T., Redman-White, W., Ashburn, P., Tan, L., Buiu, O. and Hall, S. (2008) Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture. 38th European Solid-State Device Research Conference (ESSDERC 2008), United Kingdom. 15 - 19 Sep 2008. 4 pp .

Record type: Conference or Workshop Item (Other)

Abstract

We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80mV/decade and DIBL of 30-35mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.

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Published date: September 2008
Venue - Dates: 38th European Solid-State Device Research Conference (ESSDERC 2008), United Kingdom, 2008-09-15 - 2008-09-19
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 266365
URI: https://eprints.soton.ac.uk/id/eprint/266365
PURE UUID: 7e2a54a0-5ccb-48bd-bd03-9a5bba99834e

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Date deposited: 25 Jul 2008 11:07
Last modified: 18 Jul 2019 15:40

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