Tunnel barrier properties in polycrystalline-Si single-electron transistors”,
Tunnel barrier properties in polycrystalline-Si single-electron transistors”,
pp 399-402
Furuta, Y.
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Mizuta, Hiroshi
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Kamiya, T.
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Tan, Y. T.
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Nakazato, K.
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Durrani, Z. A. K.
193df358-3ef5-4cd9-8f77-359c697e839d
Taniguchi, K.
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September 2002
Furuta, Y.
2b3632d6-4ef3-4bce-a686-0e0973b35dcd
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Kamiya, T.
d52831ff-3dba-4d58-abd2-55958ebade6e
Tan, Y. T.
2a1d615d-e201-4488-8eaf-c8bef61d68aa
Nakazato, K.
b12e41d3-3527-48ed-9ecd-b38f774ba838
Durrani, Z. A. K.
193df358-3ef5-4cd9-8f77-359c697e839d
Taniguchi, K.
9e6a93cb-1569-4d99-8507-9b227531c39b
Furuta, Y., Mizuta, Hiroshi, Kamiya, T., Tan, Y. T., Nakazato, K., Durrani, Z. A. K. and Taniguchi, K.
(2002)
Tunnel barrier properties in polycrystalline-Si single-electron transistors”,.
32th European Solid-State Device Research Conference, Firenze.
.
Record type:
Conference or Workshop Item
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cpaper_058.pdf
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Published date: September 2002
Additional Information:
Event Dates: September 2002
Venue - Dates:
32th European Solid-State Device Research Conference, Firenze, 2002-09-01
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 266379
URI: http://eprints.soton.ac.uk/id/eprint/266379
PURE UUID: 8a799daf-6f2c-494f-9323-97450a57bde8
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Date deposited: 28 Jul 2008 08:22
Last modified: 14 Mar 2024 08:28
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Contributors
Author:
Y. Furuta
Author:
Hiroshi Mizuta
Author:
T. Kamiya
Author:
Y. T. Tan
Author:
K. Nakazato
Author:
Z. A. K. Durrani
Author:
K. Taniguchi
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