Yield Model Characterization for Analogue Integrated Circuit Using Pareto-Optimal Surface
Yield Model Characterization for Analogue Integrated Circuit Using Pareto-Optimal Surface
Outline
Introduction to Analogue IC Design and its challenges
Background
- Development in Analogue CAD
- Multi Objective Optimization (MOO)
- Weight Based GA
Design Algorithm
Design Experiment & Result
- OTA design
Current & Future Work
Summary
Ali, Sawal
7d5cee93-6793-49e4-a9af-b8e3d18e90af
Wilcock, Reuben
039894e9-f32d-49e0-9ebd-fb13bc489feb
Wilson, Peter
8a65c092-c197-4f43-b8fc-e12977783cb3
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
April 2008
Ali, Sawal
7d5cee93-6793-49e4-a9af-b8e3d18e90af
Wilcock, Reuben
039894e9-f32d-49e0-9ebd-fb13bc489feb
Wilson, Peter
8a65c092-c197-4f43-b8fc-e12977783cb3
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Ali, Sawal, Wilcock, Reuben, Wilson, Peter and Brown, Andrew
(2008)
Yield Model Characterization for Analogue Integrated Circuit Using Pareto-Optimal Surface.
CDNLive 2008, Munich, Germany.
Record type:
Conference or Workshop Item
(Other)
Abstract
Outline
Introduction to Analogue IC Design and its challenges
Background
- Development in Analogue CAD
- Multi Objective Optimization (MOO)
- Weight Based GA
Design Algorithm
Design Experiment & Result
- OTA design
Current & Future Work
Summary
More information
Published date: April 2008
Additional Information:
Event Dates: 28 April 2008
Venue - Dates:
CDNLive 2008, Munich, Germany, 2008-04-28
Organisations:
EEE
Identifiers
Local EPrints ID: 266473
URI: http://eprints.soton.ac.uk/id/eprint/266473
PURE UUID: 9717b6b1-70da-4736-84fb-78e80442cfcd
Catalogue record
Date deposited: 01 Aug 2008 11:27
Last modified: 14 Mar 2024 08:28
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Contributors
Author:
Sawal Ali
Author:
Reuben Wilcock
Author:
Peter Wilson
Author:
Andrew Brown
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