Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface


Ali, Sawal, Wilcock, Reuben, Wilson, Peter and Brown, Andrew (2008) Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface At IEEE International Conference on Electronics, Circuits, and Systems, Malta.

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Description/Abstract

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

Item Type: Conference or Workshop Item (Other)
Additional Information: Event Dates: August 2008
Venue - Dates: IEEE International Conference on Electronics, Circuits, and Systems, Malta, 2008-08-01
Organisations: EEE
ePrint ID: 266474
Date :
Date Event
August 2008Published
Date Deposited: 01 Aug 2008 11:37
Last Modified: 17 Apr 2017 19:02
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/266474

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