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Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface

Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface
Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface
A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.
Ali, Sawal
7d5cee93-6793-49e4-a9af-b8e3d18e90af
Wilcock, Reuben
039894e9-f32d-49e0-9ebd-fb13bc489feb
Wilson, Peter
8a65c092-c197-4f43-b8fc-e12977783cb3
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Ali, Sawal
7d5cee93-6793-49e4-a9af-b8e3d18e90af
Wilcock, Reuben
039894e9-f32d-49e0-9ebd-fb13bc489feb
Wilson, Peter
8a65c092-c197-4f43-b8fc-e12977783cb3
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0

Ali, Sawal, Wilcock, Reuben, Wilson, Peter and Brown, Andrew (2008) Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface At IEEE International Conference on Electronics, Circuits, and Systems, Malta.

Record type: Conference or Workshop Item (Other)

Abstract

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

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More information

Published date: August 2008
Additional Information: Event Dates: August 2008
Venue - Dates: IEEE International Conference on Electronics, Circuits, and Systems, Malta, 2008-08-01
Organisations: EEE

Identifiers

Local EPrints ID: 266474
URI: http://eprints.soton.ac.uk/id/eprint/266474
PURE UUID: d15e7153-30e4-4f91-90c3-1dca3931bc34

Catalogue record

Date deposited: 01 Aug 2008 11:37
Last modified: 18 Jul 2017 07:16

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Contributors

Author: Sawal Ali
Author: Reuben Wilcock
Author: Peter Wilson
Author: Andrew Brown

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