Design optimization of NEMS switches for suspended-gate single-electron transistor applications
Design optimization of NEMS switches for suspended-gate single-electron transistor applications
174-184
Pruvost, Benjamin
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Uchida, Ken
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Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, Shunri
680a9899-52bb-4adc-8594-14bb92236fec
2009
Pruvost, Benjamin
c261b14b-523d-4fa4-8822-956be90da2fb
Uchida, Ken
a8f0b2a6-4c90-429e-ab51-eed6719cccbd
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, Shunri
680a9899-52bb-4adc-8594-14bb92236fec
Pruvost, Benjamin, Uchida, Ken, Mizuta, Hiroshi and Oda, Shunri
(2009)
Design optimization of NEMS switches for suspended-gate single-electron transistor applications.
IEEE Transactions on Nanotechnology, 8 (2), .
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paper_100.pdf
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Published date: 2009
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 267209
URI: http://eprints.soton.ac.uk/id/eprint/267209
PURE UUID: bbb68659-4735-4268-9253-12072300275c
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Date deposited: 27 Mar 2009 17:07
Last modified: 14 Mar 2024 08:45
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Contributors
Author:
Benjamin Pruvost
Author:
Ken Uchida
Author:
Hiroshi Mizuta
Author:
Shunri Oda
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