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A self-aligned silicidation technology for surround-gate vertical MOSFETS

Hakim, M.M.A., Mallik, K., de Groot, C.H., Redman-White, W, Tan, L., Hall, S. and Ashburn, P. (2009) A self-aligned silicidation technology for surround-gate vertical MOSFETS At 39th European Solid-State Device Research Conference (ESSDERC 2009), Greece. 14 - 18 Sep 2009.

Record type: Conference or Workshop Item (Other)


We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm n-channel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DIBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DIBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained.

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Published date: 17 September 2009
Venue - Dates: 39th European Solid-State Device Research Conference (ESSDERC 2009), Greece, 2009-09-14 - 2009-09-18
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 267566
PURE UUID: 841bf5b5-36e0-461c-8bf4-5a634eabc28e
ORCID for C.H. de Groot: ORCID iD

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Date deposited: 15 Jun 2009 12:40
Last modified: 24 Jul 2017 16:40

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Author: M.M.A. Hakim
Author: K. Mallik
Author: C.H. de Groot ORCID iD
Author: W Redman-White
Author: L. Tan
Author: S. Hall
Author: P. Ashburn

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