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A self-aligned silicidation technology for surround-gate vertical MOSFETS

A self-aligned silicidation technology for surround-gate vertical MOSFETS
A self-aligned silicidation technology for surround-gate vertical MOSFETS
We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120nm nchannel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DlBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DlBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mVIV. For an 80 nm channel length, a 43% improvement in the drive current is obtained.
vertical mosfets, silicidation
978-981
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Mallik, K.
c9c1ba23-0c13-4f61-b0c5-de3120d878f9
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Redman-White, W
d5376167-c925-460f-8e9c-13bffda8e0bf
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hall, S.
92b937f4-d354-4aab-871b-b0e8b6018a1d
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Mallik, K.
c9c1ba23-0c13-4f61-b0c5-de3120d878f9
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Redman-White, W
d5376167-c925-460f-8e9c-13bffda8e0bf
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hall, S.
92b937f4-d354-4aab-871b-b0e8b6018a1d
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Hakim, M.M.A., Mallik, K., de Groot, C.H., Redman-White, W, Tan, L., Hall, S. and Ashburn, P. (2009) A self-aligned silicidation technology for surround-gate vertical MOSFETS. 39th European Solid-State Device Research Conference (ESSDERC 2009), Greece. 14 - 18 Sep 2009. pp. 978-981 .

Record type: Conference or Workshop Item (Poster)

Abstract

We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120nm nchannel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DlBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DlBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mVIV. For an 80 nm channel length, a 43% improvement in the drive current is obtained.

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More information

Published date: 17 September 2009
Venue - Dates: 39th European Solid-State Device Research Conference (ESSDERC 2009), Greece, 2009-09-14 - 2009-09-18
Keywords: vertical mosfets, silicidation
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 267566
URI: https://eprints.soton.ac.uk/id/eprint/267566
PURE UUID: 841bf5b5-36e0-461c-8bf4-5a634eabc28e
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 15 Jun 2009 12:40
Last modified: 10 Sep 2019 00:47

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