Repair Techniques for Hybrid Nano/CMOS Computational Architecture
Repair Techniques for Hybrid Nano/CMOS Computational Architecture
Abstract—Presence of high defect rate in nanofabrics due to the inadequate fabrication processes has held back the development of emerging technology architecture. In this work, we propose two repair techniques to provide high level of defect tolerance in lookup table (LUT) based Boolean logic approach implemented in nano/CMOS. Further, we demonstrate that direct application of memory repair techniques is ineffective in dealing with high defect rate in hybrid nano/CMOS architecture. We show that the proposed techniques are capable of handling more than 20% defect rate in hybrid nano/CMOS architecture with efficient utilization of spare units.
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
28 July 2009
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Srivastava, Saket, Melouki, Aissa and Al-Hashimi, Bashir
(2009)
Repair Techniques for Hybrid Nano/CMOS Computational Architecture.
IEEE Conference on Nanotechnology, IEEE NANO 2009, Genoa, Italy.
26 - 31 Jul 2009.
Record type:
Conference or Workshop Item
(Poster)
Abstract
Abstract—Presence of high defect rate in nanofabrics due to the inadequate fabrication processes has held back the development of emerging technology architecture. In this work, we propose two repair techniques to provide high level of defect tolerance in lookup table (LUT) based Boolean logic approach implemented in nano/CMOS. Further, we demonstrate that direct application of memory repair techniques is ineffective in dealing with high defect rate in hybrid nano/CMOS architecture. We show that the proposed techniques are capable of handling more than 20% defect rate in hybrid nano/CMOS architecture with efficient utilization of spare units.
Text
ieee_nano_final.pdf
- Accepted Manuscript
More information
Published date: 28 July 2009
Additional Information:
Event Dates: July 26-31
Venue - Dates:
IEEE Conference on Nanotechnology, IEEE NANO 2009, Genoa, Italy, 2009-07-26 - 2009-07-31
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 267657
URI: http://eprints.soton.ac.uk/id/eprint/267657
PURE UUID: c48c9460-3d92-4647-9194-283e0087a129
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Date deposited: 09 Jul 2009 13:24
Last modified: 14 Mar 2024 08:55
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Contributors
Author:
Saket Srivastava
Author:
Aissa Melouki
Author:
Bashir Al-Hashimi
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