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Double-polysilicon self-aligned lateral bipolar transistors

Double-polysilicon self-aligned lateral bipolar transistors
Double-polysilicon self-aligned lateral bipolar transistors
A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances(CJCS0) around 1.3–2.6 fF (substrate is ground). A SOI thickness of 0.2–0.5 μm combined with 0.13–0.25 μm lithography could allow a reduction of transistor dimensions down to (0.2–0.5) · (0.13–0.25) lm2 and give an estimated minimum emitter/base junction capacitance(CJE0) of 0.54–1.36 fF. Simple device isolation is predicted to produce a small collector/base junction capacitance (CJC0) of 0.42–2.00 fF. Furthermore, use of a double base contact can help reduce base resistance (RB) to 0.43–1.17 kW and a wide collector window directly contacted to the collector is estimated to result in around 0.66–1.58 kW collector resistance (RC). By taking all parameters into account a cut-off frequency (fT) of 69–116 GHz and maximum oscillation frequency (fmax) of 61–128 GHz is predicted for this design, in addition a gain of 47–101(using minimum gain enhancement) and roughly 10.6–21.0 ps ECL propagation delay time, at a current of 0.4–1.0 mA could be achieved. Our simulations indicate that this new doubled-polysilicon self-aligned structure could outperform all other silicon bipolar transistors that have been reported.
183-187
Pengpad, P.
ac3c8c12-6fee-4677-b9c7-2db6be43d09b
Bagnall, D.M.
5d84abc8-77e5-43f7-97cb-e28533f25ef1
Pengpad, P.
ac3c8c12-6fee-4677-b9c7-2db6be43d09b
Bagnall, D.M.
5d84abc8-77e5-43f7-97cb-e28533f25ef1

Pengpad, P. and Bagnall, D.M. (2008) Double-polysilicon self-aligned lateral bipolar transistors. Journal of Materials Science: Materials in Electronics, 19, 183-187.

Record type: Article

Abstract

A new lateral bipolar junction transistor that utilises a double-polysilicon self-aligned structure to maximise high-frequency performance is introduced. Silicon-on-oxide (SOI) wafers are used to isolate devices from the substrate and to minimise parasitic substrate capacitances(CJCS0) around 1.3–2.6 fF (substrate is ground). A SOI thickness of 0.2–0.5 μm combined with 0.13–0.25 μm lithography could allow a reduction of transistor dimensions down to (0.2–0.5) · (0.13–0.25) lm2 and give an estimated minimum emitter/base junction capacitance(CJE0) of 0.54–1.36 fF. Simple device isolation is predicted to produce a small collector/base junction capacitance (CJC0) of 0.42–2.00 fF. Furthermore, use of a double base contact can help reduce base resistance (RB) to 0.43–1.17 kW and a wide collector window directly contacted to the collector is estimated to result in around 0.66–1.58 kW collector resistance (RC). By taking all parameters into account a cut-off frequency (fT) of 69–116 GHz and maximum oscillation frequency (fmax) of 61–128 GHz is predicted for this design, in addition a gain of 47–101(using minimum gain enhancement) and roughly 10.6–21.0 ps ECL propagation delay time, at a current of 0.4–1.0 mA could be achieved. Our simulations indicate that this new doubled-polysilicon self-aligned structure could outperform all other silicon bipolar transistors that have been reported.

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Published date: 2008
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 267720
URI: https://eprints.soton.ac.uk/id/eprint/267720
PURE UUID: bddf34f8-73df-4210-8e06-64eb5aa900d9

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Date deposited: 29 Jul 2009 11:06
Last modified: 19 Jul 2019 22:17

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Contributors

Author: P. Pengpad
Author: D.M. Bagnall

University divisions

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