Design of new logic architectures utilizing optimized suspended-gate single-electron transistors
Design of new logic architectures utilizing optimized suspended-gate single-electron transistors
The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.
504-512
Pruvost, B.
9e5e3a90-fe6f-467e-ac42-ebfca7811e57
Uchida, K.
94591838-45bd-426b-91da-f9d60a055c6c
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, S.
514339b3-f8de-4750-8d20-c520834b2477
2010
Pruvost, B.
9e5e3a90-fe6f-467e-ac42-ebfca7811e57
Uchida, K.
94591838-45bd-426b-91da-f9d60a055c6c
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Oda, S.
514339b3-f8de-4750-8d20-c520834b2477
Pruvost, B., Uchida, K., Mizuta, Hiroshi and Oda, S.
(2010)
Design of new logic architectures utilizing optimized suspended-gate single-electron transistors.
IEEE Transactions on Nanotechnology, 9 (4), .
(doi:10.1109/TNANO.2009.2030502).
Abstract
The operation and performances of the suspended-gate single-electron transistor (SET) are investigated through simulation. The movable gate is 3-D optimized, so that low actuation voltage (0.4 V), fast switching (1 ns), and ultralow pull-in energy (0.015 fJ) are simulated. A two-state capacitor model based on the 3-D results is then embedded with a SET analytical model in a SPICE environment to investigate the operation of the device. Through the control of the Coulomb oscillation characteristics, the position of the movable gate enables a background charge insensitive coding of the information. New circuit architectures with applications in cellular nonlinear network and pattern matching are also proposed and simulated.
Text
Design_of_New_Logic_Architectures_utilizing_SG-SETs.pdf
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e-pub ahead of print date: 25 August 2009
Published date: 2010
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 267766
URI: http://eprints.soton.ac.uk/id/eprint/267766
PURE UUID: b6e36b5f-aeff-4013-9a4e-8a9de7eccec9
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Date deposited: 10 Aug 2009 11:52
Last modified: 14 Mar 2024 08:58
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Contributors
Author:
B. Pruvost
Author:
K. Uchida
Author:
Hiroshi Mizuta
Author:
S. Oda
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