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Design of New Logic Architectures Utilizing Optimized Suspended-Gate Single-Electron Transistors

Pruvost, B, Uchida, K, Mizuta, Hiroshi and Oda, S (2009) Design of New Logic Architectures Utilizing Optimized Suspended-Gate Single-Electron Transistors IEEE Transactions on Nanotechnology

Record type: Article
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Published date: 2009
Organisations: Nanoelectronics and Nanotechnology

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Local EPrints ID: 267766
URI: http://eprints.soton.ac.uk/id/eprint/267766
PURE UUID: b6e36b5f-aeff-4013-9a4e-8a9de7eccec9

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Date deposited: 10 Aug 2009 11:52
Last modified: 18 Jul 2017 07:00

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Contributors

Author: B Pruvost
Author: K Uchida
Author: Hiroshi Mizuta
Author: S Oda

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