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Impact of NBTI on the Performance of 35nm CMOS Digital Circuits

Record type: Article

The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters, as well as the static noise margin degradation of the SRAM are analysed. Moreover, the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.

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Citation

Wang, YG and Zwolinski, M (2008) Impact of NBTI on the Performance of 35nm CMOS Digital Circuits 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, pp. 440-443.

More information

Published date: 2008
Additional Information: Imported from ISI Web of Science
Organisations: EEE

Identifiers

Local EPrints ID: 269544
URI: http://eprints.soton.ac.uk/id/eprint/269544
PURE UUID: 80bfa47d-9704-4697-be7f-e1e7fffd448a
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 21 Apr 2010 07:46
Last modified: 18 Jul 2017 06:51

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Contributors

Author: YG Wang
Author: M Zwolinski ORCID iD

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