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Impact of NBTI on the Performance of 35nm CMOS Digital Circuits

Wang, Yangang and Zwolinski, M (2008) Impact of NBTI on the Performance of 35nm CMOS Digital Circuits In 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. IEEE., pp. 440-443. (doi:10.1109/ICSICT.2008.4734569).

Record type: Conference or Workshop Item (Paper)


The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters, as well as the static noise margin degradation of the SRAM are analysed. Moreover, the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.

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Published date: 2008
Additional Information: Imported from ISI Web of Science
Organisations: EEE


Local EPrints ID: 269544
PURE UUID: 80bfa47d-9704-4697-be7f-e1e7fffd448a
ORCID for M Zwolinski: ORCID iD

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Date deposited: 21 Apr 2010 07:46
Last modified: 06 Sep 2017 16:31

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Author: Yangang Wang
Author: M Zwolinski ORCID iD

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