Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance
Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance
In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, Rd and Rs from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency fT, until the on-current Ion becomes limited by increasing series resistances and fT therefore reduces. The results indicate a thickness of 40nm FILOX for maximum fT. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.
vertical MOSFETs, source/drain resistance, overlap capacitance
187-190
Tan, L.
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Hall, S.
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Buiu, O.
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Hakim, M.M.A.
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Uchino, T.
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Ashburn, P.
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Redman-White, W.
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2008
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Hall, S.
92b937f4-d354-4aab-871b-b0e8b6018a1d
Buiu, O.
a994b22e-018b-4355-abd5-0227724f2a1a
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Uchino, T.
706196b8-2f2c-403d-97aa-2995eac8572b
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Tan, L., Hall, S., Buiu, O., Hakim, M.M.A., Uchino, T., Ashburn, P. and Redman-White, W.
(2008)
Series resistance in vertical MOSFETs with reduced drain/source overlap capacitance.
9th International Conference on Ultimate Integration of Silicon (ULIS 2008), Udine, Italy.
12 - 14 Mar 2008.
.
Record type:
Conference or Workshop Item
(Poster)
Abstract
In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet local oxidation (FILOX) structure that serves to reduce the gate to drain/source overlap capacitances. The series resistances are modeled analytically and the important influencing factors, namely gate bias dependence and the asymmetric nature of the device, are identified. We extract by simulation, Rd and Rs from devices with different FILOX thicknesses, employing an impedance method often used in RF characterisation. We identify the trade-off whereby thickening the FILOX first causes an increase of the cut-off frequency fT, until the on-current Ion becomes limited by increasing series resistances and fT therefore reduces. The results indicate a thickness of 40nm FILOX for maximum fT. We also investigate the influence of process conditions on low series resistances, namely time of rapid thermal annealing RTA and angle of implantation.
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2008_Tan_ULIS_VMOS_series_resistance.pdf
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More information
Published date: 2008
Venue - Dates:
9th International Conference on Ultimate Integration of Silicon (ULIS 2008), Udine, Italy, 2008-03-12 - 2008-03-14
Keywords:
vertical MOSFETs, source/drain resistance, overlap capacitance
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 270866
URI: http://eprints.soton.ac.uk/id/eprint/270866
PURE UUID: 615a97a2-c62f-4f9a-a45c-23baa791ce43
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Date deposited: 21 Apr 2010 01:26
Last modified: 14 Mar 2024 09:17
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Contributors
Author:
L. Tan
Author:
S. Hall
Author:
O. Buiu
Author:
M.M.A. Hakim
Author:
T. Uchino
Author:
W. Redman-White
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