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Modeling the Impact of Process Variation on Resistive Bridge Defects

Record type: Conference or Workshop Item (Paper)

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V) and effective mobility (ueff) where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.

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Citation

Khursheed, Syed Saqib, Zhong, Shida, Al-Hashimi, Bashir, Aitken, Robert and Kundu, Sandip (2010) Modeling the Impact of Process Variation on Resistive Bridge Defects At International Test Conference, United States.

More information

Published date: November 2010
Venue - Dates: International Test Conference, United States, 2010-11-01
Organisations: Electronic & Software Systems, EEE

Identifiers

Local EPrints ID: 271480
URI: http://eprints.soton.ac.uk/id/eprint/271480
PURE UUID: a6b9cd4c-6d98-4441-8240-02dcf10c01df

Catalogue record

Date deposited: 11 Aug 2010 17:10
Last modified: 18 Jul 2017 06:42

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Contributors

Author: Syed Saqib Khursheed
Author: Shida Zhong
Author: Robert Aitken
Author: Sandip Kundu

University divisions

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