The University of Southampton
University of Southampton Institutional Repository

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications
Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications
We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.
VMOS, silicides, vertical MOSFET, CMOS, RF
3318-3326
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Abuelgasim, A.
eaa5e29e-510d-45e4-a724-d7f69c05f853
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038
Hakim, M.M.A.
e584d902-b647-49eb-85bf-15446c06652a
Tan, L.
93a93652-be22-48a3-b4d0-b4e6605088d5
Abuelgasim, A.
eaa5e29e-510d-45e4-a724-d7f69c05f853
de Groot, C.H.
92cd2e02-fcc4-43da-8816-c86f966be90c
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Hall, S.
a11a8f8b-d6fb-47a7-82b1-1f76d2f170dc
Ashburn, P.
68cef6b7-205b-47aa-9efb-f1f09f5c1038

Hakim, M.M.A., Tan, L., Abuelgasim, A., de Groot, C.H., Redman-White, W., Hall, S. and Ashburn, P. (2010) Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications. IEEE Transactions on Electron Devices, 57 (12), 3318-3326. (doi:10.1109/TED.2010.2082293).

Record type: Article

Abstract

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Text
2010_Hakim_silicided_VMOS_TED.pdf - Version of Record
Download (1MB)

More information

Published date: December 2010
Keywords: VMOS, silicides, vertical MOSFET, CMOS, RF
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 271772
URI: https://eprints.soton.ac.uk/id/eprint/271772
PURE UUID: 9c362f04-ade1-4a41-a47b-478f35d22755
ORCID for C.H. de Groot: ORCID iD orcid.org/0000-0002-3850-7101

Catalogue record

Date deposited: 13 Dec 2010 16:09
Last modified: 05 Nov 2019 01:53

Export record

Altmetrics

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of https://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×