Statistical power analysis for nanoscale CMOS

Wang, Yangang, Merrett, M. and Zwolinski, M. (2010) Statistical power analysis for nanoscale CMOS. 2010 International Conference on Signals and Electronic Systems (ICSES). pp. 201-204 .

Record type: Conference or Workshop Item (Other)

Abstract

With the scaling down of CMOS technology, process variations are becoming significant. Power consumption is a major constraint on IC yield. However, there has been little research on statistical power analysis compared with that on timing analysis. Here, both the static and dynamic power are considered. We characterize a cell library containing mean power. A standard deviation power library is extracted from Monte Carlo simulations. Then, the mean and variance of the power are derived. The proposed technique is validated on benchmark circuits at 35 nm. We compare the results with SPICE simulations and show that the difference is acceptable.

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Published date: September 2010

Additional Information: 2010 International Conference on Signals and Electronic Systems (ICSES), 7-10 September 2010, Gliwice, Poland

Venue - Dates: 2010 International Conference on Signals and Electronic Systems (ICSES), 2010-09-01

Keywords: Practical, Theoretical or Mathematical/ CMOS integrated circuits, Monte Carlo methods, nanoelectronics, power integrated circuits, statistical analysis/ statistical power analysis, nanoscale CMOS, power consumption, static power, dynamic power, cell library, mean power, Monte Carlo simulation, size 35 nm/ B2570D CMOS integrated circuits, B2570P Power integrated circuits, B0240G Monte Carlo methods/ size 3.5E-08 m

Organisations: EEE