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Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation

Hakim, M M A, Tan, L., Buiu, O., Redman-White, W., Hall, S. and Ashburn, P (2009) Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation Solid State Electronics, 53, (7), pp. 753-759. (doi:10.1016/j.sse.2009.02.016).

Record type: Article


This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of sub-threshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76 mV/dec and a DIBL of 33 mV/V at a channel length of 100 nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81 mV/dec and a DIBL of 25 mV/V at a channel length of 100 nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process

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Published date: July 2009
Organisations: Nanoelectronics and Nanotechnology


Local EPrints ID: 272584
ISSN: 0038-1101
PURE UUID: f7f8b2df-10eb-41d7-b33e-d234c27568d2

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Date deposited: 20 Jul 2011 00:12
Last modified: 18 Jul 2017 06:22

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Author: M M A Hakim
Author: L. Tan
Author: O. Buiu
Author: W. Redman-White
Author: S. Hall
Author: P Ashburn

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