The University of Southampton
University of Southampton Institutional Repository

Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders

Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders
Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders
Low Density Parity Check (LDPC) decoders have an inherent capability of correcting the transmission errors that occur, when communicating over a hostile wireless channel. This capability allows LDPC-coded schemes to employ lower transmission energies than uncoded schemes, at the cost of introducing a significant processing energy consumption during LDPC decoding. Traditional energy-reduction techniques, such as voltage and clock scaling can be employed for reducing the LDPC decoder’s energy consumption. However, these techniques may induce timing errors, which can degrade the LDPC decoder’s error correction capability. Our previous work has demonstrated that in contrast to other types of LDPC decoders, stochastic decoders have an inherent tolerance to timing errors, allowing them to maintain a high error correction capability in clock- scaling scenarios. In this paper, we investigate this timing error tolerance in voltage-scaling scenarios, by extending our previous model of timing errors using extensive SPICE simulations. Furthermore, we use these SPICE simulations to characterize the processing energy consumption of stochastic LDPC decoders for the first time. We demonstrate that a modified stochastic LDPC decoder can operate at 0.8 V and a clock period of 915.11 ps, while maintaining the error correction capability of a conventional stochastic decoder operating at 1 V and a clock period of 1019.2 ps, offering a 36.7% reduction in processing energy consumption.
978-1-4673-5937-5
4293-4298
Perez-Andrade, I.
6f06718b-0d0f-4849-9b4e-3bff757614cc
Zuo, X.
ae6db77f-19f4-4f8b-aea3-22b5cdc1da26
Maunder, R.G.
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, L.
66e7266f-3066-4fc0-8391-e000acce71a1
Perez-Andrade, I.
6f06718b-0d0f-4849-9b4e-3bff757614cc
Zuo, X.
ae6db77f-19f4-4f8b-aea3-22b5cdc1da26
Maunder, R.G.
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, B.M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, L.
66e7266f-3066-4fc0-8391-e000acce71a1

Perez-Andrade, I., Zuo, X., Maunder, R.G., Al-Hashimi, B.M. and Hanzo, L. (2013) Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders At 2013 IEEE Wireless Communications and Networking Conference (WCNC), China. 07 - 10 Apr 2013. , pp. 4293-4298.

Record type: Conference or Workshop Item (Paper)

Abstract

Low Density Parity Check (LDPC) decoders have an inherent capability of correcting the transmission errors that occur, when communicating over a hostile wireless channel. This capability allows LDPC-coded schemes to employ lower transmission energies than uncoded schemes, at the cost of introducing a significant processing energy consumption during LDPC decoding. Traditional energy-reduction techniques, such as voltage and clock scaling can be employed for reducing the LDPC decoder’s energy consumption. However, these techniques may induce timing errors, which can degrade the LDPC decoder’s error correction capability. Our previous work has demonstrated that in contrast to other types of LDPC decoders, stochastic decoders have an inherent tolerance to timing errors, allowing them to maintain a high error correction capability in clock- scaling scenarios. In this paper, we investigate this timing error tolerance in voltage-scaling scenarios, by extending our previous model of timing errors using extensive SPICE simulations. Furthermore, we use these SPICE simulations to characterize the processing energy consumption of stochastic LDPC decoders for the first time. We demonstrate that a modified stochastic LDPC decoder can operate at 0.8 V and a clock period of 915.11 ps, while maintaining the error correction capability of a conventional stochastic decoder operating at 1 V and a clock period of 1019.2 ps, offering a 36.7% reduction in processing energy consumption.

PDF Stochastic_LDPC_VFS.pdf - Accepted Manuscript
Download (7MB)
PDF WCNC.pdf - Other
Download (9MB)

More information

Submitted date: 10 October 2012
Accepted/In Press date: 14 December 2012
Published date: 7 April 2013
Venue - Dates: 2013 IEEE Wireless Communications and Networking Conference (WCNC), China, 2013-04-07 - 2013-04-10
Organisations: Electronic & Software Systems, Southampton Wireless Group

Identifiers

Local EPrints ID: 344044
URI: http://eprints.soton.ac.uk/id/eprint/344044
ISBN: 978-1-4673-5937-5
PURE UUID: dd954e61-a8cd-4b20-b0c7-7039f968012b
ORCID for R.G. Maunder: ORCID iD orcid.org/0000-0002-7944-2615
ORCID for L. Hanzo: ORCID iD orcid.org/0000-0002-2636-5214

Catalogue record

Date deposited: 11 Oct 2012 09:15
Last modified: 08 Nov 2017 04:10

Export record

Contributors

Author: I. Perez-Andrade
Author: X. Zuo
Author: R.G. Maunder ORCID iD
Author: B.M. Al-Hashimi
Author: L. Hanzo ORCID iD

University divisions

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×