A multi-voltage aware resistive open fault model

Abstract

Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.
The presented model is expected to substantially enhance multi-voltage test generation and fault distinction

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Identifiers

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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