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A multi-voltage aware resistive open fault model

A multi-voltage aware resistive open fault model
A multi-voltage aware resistive open fault model
Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.
The presented model is expected to substantially enhance multi-voltage test generation and fault distinction
1063-8210
220-231
Mohammadat, Mohamed Tagelsir
ca863f82-214c-476b-b77d-95b5d8c1f9e1
Zain Ali, Noohul Basheer
845c9da7-dce4-4965-a7a3-b920e965d82f
Hussin, Fawnizu Azmadi
b38a423d-15d8-4cdb-89c7-f796246152fc
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Mohammadat, Mohamed Tagelsir
ca863f82-214c-476b-b77d-95b5d8c1f9e1
Zain Ali, Noohul Basheer
845c9da7-dce4-4965-a7a3-b920e965d82f
Hussin, Fawnizu Azmadi
b38a423d-15d8-4cdb-89c7-f796246152fc
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Mohammadat, Mohamed Tagelsir, Zain Ali, Noohul Basheer, Hussin, Fawnizu Azmadi and Zwolinski, Mark (2014) A multi-voltage aware resistive open fault model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22 (2), 220-231. (doi:10.1109/TVLSI.2013.2243926).

Record type: Article

Abstract

Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs {causing delay failures and reliability-related concerns}. The widespread utilization of multiple supply voltages in contemporary VLSI designs and {emerging test methods} poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the $V_{DD}$ effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observed that the detectable resistance range versus $V_{DD}$ varies with test speed. We consequently propose a voltage-aware model which divides the full range of open resistances ($RO$) into continuous behavioral intervals and three detectability ranges.
The presented model is expected to substantially enhance multi-voltage test generation and fault distinction

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Published date: February 2014
Organisations: EEE

Identifiers

Local EPrints ID: 347675
URI: http://eprints.soton.ac.uk/id/eprint/347675
ISSN: 1063-8210
PURE UUID: 3ce82e2d-646c-4d05-9334-ea34e9ac516a
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 28 Jan 2013 21:32
Last modified: 12 Nov 2019 02:04

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Contributors

Author: Mohamed Tagelsir Mohammadat
Author: Noohul Basheer Zain Ali
Author: Fawnizu Azmadi Hussin
Author: Mark Zwolinski ORCID iD

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