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Overview of the SpiNNaker system architecture

Furber, Steve, Lester, David, Plana, Luis, Garside, Jim, Painkras, Eustace, Temple, Steve and Brown, A.D. (2012) Overview of the SpiNNaker system architecture IEEE Transactions on Computers, 99, pp. 1-14. (doi:10.1109/TC.2012.142).

Record type: Article


SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behaviour of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principle axioms of parallel machine design - memory coherence, synchronicity and determinism - have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgement, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the description.

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Published date: 12 June 2012
Keywords: interconnection architectures, parallel processors, neurocomputers, real-time distributed
Organisations: EEE


Local EPrints ID: 350495
PURE UUID: 1b13ca62-1ff8-4b14-91ee-485995883e0d

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Date deposited: 04 Apr 2013 13:05
Last modified: 18 Jul 2017 04:34

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Author: Steve Furber
Author: David Lester
Author: Luis Plana
Author: Jim Garside
Author: Eustace Painkras
Author: Steve Temple
Author: A.D. Brown

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