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CMOS compatible vertical surround gate mosfets with reduced parasitics

CMOS compatible vertical surround gate mosfets with reduced parasitics
CMOS compatible vertical surround gate mosfets with reduced parasitics
The international technology roadmap for semiconductors predicts that downscaling of the dimensions of electronic devices will continue according to Moore's law for the next 10 to 15 years. However, device scaling is getting more and more complicated due to physical limitations. Novel device architectures are needed to overcome these problems. Vertical transistors could be one potential solution since the channel length is independent from the device layout.

In this thesis, novel concepts to reduce parasitic behaviour in vertical single and surround gate MOSFETs are presented. This includes a novel fillet local oxidation (FILOX) process, optimisations of the pillar, a pillar top insulator and the incorporation of polySiGe into the source of a vertical MOS transistor.

Calculations based on industry layout rules at the l00nm technology node for vertical and lateral devices are presented. For the optimised minimum geometry single gate vertical MOSFET incorporating FILOX with optimised pillar structure, the gate/drain capacitance is 40% and the gate/source overlap capacitance 60% of that of a minimum dimension lateral MOS device. For optimised surround gate transistors the overlap capacitance is 20% and 5% of that of a lateral transistor. These calculations demonstrate the potential of optimised vertical MOS transistors.

Pillar capacitors incorporating the FILOX process have been fabricated and a reduction in the measured capacitance is obtained by a factor of 1.4 and 5.6 for structures with nitride top and nitride top and FILOX, respectively. Device simulations confirm the measured reduction in capacitance. The extracted oxide thickness on the pillar sidewall is 9.3nm for the fabricated structures, which agrees within a factor of 1.18 with the simulated oxide thickness on the sidewall. Kinks in CV measurements have been investigated and explained by the formation of an inversion layer underneath the field oxide.

A low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses FILOX to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Fabricated n-channel devices show subthreshold slopes of 111 and 123mV/decade for 3nm gate oxide thickness and a channel length of about 105nm for single and surround gate devices, respectively. The devices show good symmetry between the source on top and source on bottom configuration.
Kunz, Veit Dominik
7c238b9e-33d2-4ce8-9cd8-ab0b9f824fd7
Kunz, Veit Dominik
7c238b9e-33d2-4ce8-9cd8-ab0b9f824fd7
Ashburn, Peter
68cef6b7-205b-47aa-9efb-f1f09f5c1038

(2003) CMOS compatible vertical surround gate mosfets with reduced parasitics. University of Southampton, Electronics and Computer Science, Doctoral Thesis, 206pp.

Record type: Thesis (Doctoral)

Abstract

The international technology roadmap for semiconductors predicts that downscaling of the dimensions of electronic devices will continue according to Moore's law for the next 10 to 15 years. However, device scaling is getting more and more complicated due to physical limitations. Novel device architectures are needed to overcome these problems. Vertical transistors could be one potential solution since the channel length is independent from the device layout.

In this thesis, novel concepts to reduce parasitic behaviour in vertical single and surround gate MOSFETs are presented. This includes a novel fillet local oxidation (FILOX) process, optimisations of the pillar, a pillar top insulator and the incorporation of polySiGe into the source of a vertical MOS transistor.

Calculations based on industry layout rules at the l00nm technology node for vertical and lateral devices are presented. For the optimised minimum geometry single gate vertical MOSFET incorporating FILOX with optimised pillar structure, the gate/drain capacitance is 40% and the gate/source overlap capacitance 60% of that of a minimum dimension lateral MOS device. For optimised surround gate transistors the overlap capacitance is 20% and 5% of that of a lateral transistor. These calculations demonstrate the potential of optimised vertical MOS transistors.

Pillar capacitors incorporating the FILOX process have been fabricated and a reduction in the measured capacitance is obtained by a factor of 1.4 and 5.6 for structures with nitride top and nitride top and FILOX, respectively. Device simulations confirm the measured reduction in capacitance. The extracted oxide thickness on the pillar sidewall is 9.3nm for the fabricated structures, which agrees within a factor of 1.18 with the simulated oxide thickness on the sidewall. Kinks in CV measurements have been investigated and explained by the formation of an inversion layer underneath the field oxide.

A low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses FILOX to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Fabricated n-channel devices show subthreshold slopes of 111 and 123mV/decade for 3nm gate oxide thickness and a channel length of about 105nm for single and surround gate devices, respectively. The devices show good symmetry between the source on top and source on bottom configuration.

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Published date: April 2003
Organisations: University of Southampton, Electronics & Computer Science

Identifiers

Local EPrints ID: 362439
URI: http://eprints.soton.ac.uk/id/eprint/362439
PURE UUID: 604ebc7a-49c9-4555-b739-376411b17675

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Date deposited: 24 Feb 2014 13:41
Last modified: 18 Jul 2017 02:52

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Contributors

Author: Veit Dominik Kunz
Thesis advisor: Peter Ashburn

University divisions

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