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Resistive open faults detectability analysis and implications for testing low power nanometric ICs

Resistive open faults detectability analysis and implications for testing low power nanometric ICs
Resistive open faults detectability analysis and implications for testing low power nanometric ICs
Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.
580-583
Mohammadat, M.T.
d07c38ce-4db6-42f4-be6e-e3a3ba2cb0aa
Ali, N.B.Z.
fe2ef65d-b30e-45cb-a9fe-7f23abe2b2ae
Hussin, F.A.
3d7a2444-4c86-4232-80ae-cd3eebd090a6
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Mohammadat, M.T.
d07c38ce-4db6-42f4-be6e-e3a3ba2cb0aa
Ali, N.B.Z.
fe2ef65d-b30e-45cb-a9fe-7f23abe2b2ae
Hussin, F.A.
3d7a2444-4c86-4232-80ae-cd3eebd090a6
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Mohammadat, M.T., Ali, N.B.Z., Hussin, F.A. and Zwolinski, M. (2015) Resistive open faults detectability analysis and implications for testing low power nanometric ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23 (3), 580-583. (doi:10.1109/TVLSI.2014.2312357).

Record type: Article

Abstract

Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.

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e-pub ahead of print date: 3 April 2014
Published date: 20 March 2015
Organisations: EEE

Identifiers

Local EPrints ID: 364712
URI: http://eprints.soton.ac.uk/id/eprint/364712
PURE UUID: 0afe11fb-8b81-4bf3-bceb-92d6eca05c7f
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 09 May 2014 14:12
Last modified: 20 Jul 2019 01:26

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