Error correcting code analysis for cache memory high reliability and performance
Error correcting code analysis for cache memory high reliability and performance
In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/code-segment size for a given application.
cache storage, error correction codes
978-3-9810801-7-9
1-6
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Timoncini, Nicola
b77f2a44-c761-4e74-a929-1998e5e794af
Spica, Michael
7cc071e0-35ab-4cb1-928f-17c93ccc4d82
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Timoncini, Nicola
b77f2a44-c761-4e74-a929-1998e5e794af
Spica, Michael
7cc071e0-35ab-4cb1-928f-17c93ccc4d82
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Rossi, Daniele, Timoncini, Nicola, Spica, Michael and Metra, Cecilia
(2011)
Error correcting code analysis for cache memory high reliability and performance.
IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, France.
14 - 18 Mar 2011.
.
(doi:10.1109/DATE.2011.5763257).
Record type:
Conference or Workshop Item
(Paper)
Abstract
In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/code-segment size for a given application.
Text
date11.pdf
- Accepted Manuscript
More information
e-pub ahead of print date: March 2011
Venue - Dates:
IEEE/ACM Design, Automation and Test in Europe (DATE), Grenoble, France, 2011-03-14 - 2011-03-18
Keywords:
cache storage, error correction codes
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368913
URI: http://eprints.soton.ac.uk/id/eprint/368913
ISBN: 978-3-9810801-7-9
PURE UUID: 8f160214-312e-4491-a576-a991e20d4389
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Date deposited: 16 Sep 2014 17:03
Last modified: 14 Mar 2024 17:55
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Contributors
Author:
Daniele Rossi
Author:
Nicola Timoncini
Author:
Michael Spica
Author:
Cecilia Metra
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