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SpiNNaker - programming model

SpiNNaker - programming model
SpiNNaker - programming model
SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 216x18=1179648 cores. This remarkable property is achieved at the cost of ignoring memory coherency, global synchronisation and even deterministic message passing, yet it is still possible to perform meaningful computations. Whilst we have yet to assemble the full machine, the scalability properties make it possible to demonstrate the capabilities of the machine whilst it is being assembled; the more cores we connect, the larger the problems become that we are able to attack. Even with isolated printed circuit boards of 864 cores, interesting capabilities are emerging. This paper is the third of a series charting the development trajectory of the system. In the first two, we outlined the hardware build. Here, we lay out the (rather unusual) low-level foundation software developed so far to support the operation of the machine.
interconnection architectures, parallel processors, neurocomputers, real-time distributed
1769-1782
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Reeve, J.S.
dd909010-7d44-44ea-83fe-a09e4d492618
Garside, J.D.
d0e3e42e-4285-4b8b-bad3-1068d150060a
Dugan, K.J.
c04b7dde-41c9-4dee-bba3-06918eac18ae
Plana, L.A.
e0db7215-9f83-4dab-bf8e-863d61e47d16
Temple, S.
bd41170c-d02e-49bd-a80a-d75c3933ca1f
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Reeve, J.S.
dd909010-7d44-44ea-83fe-a09e4d492618
Garside, J.D.
d0e3e42e-4285-4b8b-bad3-1068d150060a
Dugan, K.J.
c04b7dde-41c9-4dee-bba3-06918eac18ae
Plana, L.A.
e0db7215-9f83-4dab-bf8e-863d61e47d16
Temple, S.
bd41170c-d02e-49bd-a80a-d75c3933ca1f

Brown, A.D., Reeve, J.S., Garside, J.D., Dugan, K.J., Plana, L.A. and Temple, S. (2015) SpiNNaker - programming model IEEE Transactions on Computers, 64, (6), pp. 1769-1782. (doi:10.1109/TC.2014.2329686).

Record type: Article

Abstract

SpiNNaker is a multi-core computing engine, with a bespoke and specialised communication infrastructure that supports almost perfect scalability up to a hard limit of 216x18=1179648 cores. This remarkable property is achieved at the cost of ignoring memory coherency, global synchronisation and even deterministic message passing, yet it is still possible to perform meaningful computations. Whilst we have yet to assemble the full machine, the scalability properties make it possible to demonstrate the capabilities of the machine whilst it is being assembled; the more cores we connect, the larger the problems become that we are able to attack. Even with isolated printed circuit boards of 864 cores, interesting capabilities are emerging. This paper is the third of a series charting the development trajectory of the system. In the first two, we outlined the hardware build. Here, we lay out the (rather unusual) low-level foundation software developed so far to support the operation of the machine.

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e-pub ahead of print date: 13 June 2014
Published date: June 2015
Keywords: interconnection architectures, parallel processors, neurocomputers, real-time distributed
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 369378
URI: http://eprints.soton.ac.uk/id/eprint/369378
PURE UUID: d1976fab-4177-4975-a73e-bd3cb3fb250a

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Date deposited: 25 Sep 2014 09:09
Last modified: 18 Jul 2017 01:37

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Contributors

Author: A.D. Brown
Author: J.S. Reeve
Author: J.D. Garside
Author: K.J. Dugan
Author: L.A. Plana
Author: S. Temple

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