Erasable diffractive grating couplers in silicon on insulator
Erasable diffractive grating couplers in silicon on insulator
This doctoral project investigates the design, fabrication and characterisation of germanium implanted grating couplers in silicon on insulator and their subsequent removal by laser annealing. The application for these devices is dominantly seen to be in wafer scale testing for optical integrated circuits, though the planar surface may offer benefits in other areas such as 3 dimensional optical circuits. Wafer scale testing is critical to reducing production costs and increasing production yield. In this thesis a method that allows testing of individual optical components within a complex optical integrated circuit is described. The method is based on diffractive grating couplers, which can be used to efficiently couple light from an optical fibre to a silicon waveguide. In this work gratings are fabricated by the introduction of lattice disorder, induced by ion implantation of germanium opposed to the typical surface relief structure typically used. The lattice damage alters the crystalline structure of silicon, hence causing a change in the refractive index. Coupling performance determined empirically, showed a 5.5dB loss between the fibre and planar waveguide modes, which is not dissimilar to the performance of typical uniform surface relief gratings currently used.
Gratings fabricated using this method can be erased via localised laser annealing after device testing is completed. Annealing is shown reduce the outcoupling efficiency of the gratings fabricated by ~21dB. Laser annealing was achieved by employing a continuous wave laser, operating at visible wavelengths thus reducing equipment costs compared with traditional annealing systems, which use a pulsed, deep ultra violet laser. The process developed retains CMOS compatibility which enables the design to be used in current microelectronics fabrication facilities.
University of Southampton
Topley, Robert
f43e052f-31c2-47a5-a627-3ce44fbc99a1
October 2014
Topley, Robert
f43e052f-31c2-47a5-a627-3ce44fbc99a1
Reed, G.T.
ca08dd60-c072-4d7d-b254-75714d570139
Topley, Robert
(2014)
Erasable diffractive grating couplers in silicon on insulator.
University of Southampton, Physical Sciences and Engineering, Doctoral Thesis, 160pp.
Record type:
Thesis
(Doctoral)
Abstract
This doctoral project investigates the design, fabrication and characterisation of germanium implanted grating couplers in silicon on insulator and their subsequent removal by laser annealing. The application for these devices is dominantly seen to be in wafer scale testing for optical integrated circuits, though the planar surface may offer benefits in other areas such as 3 dimensional optical circuits. Wafer scale testing is critical to reducing production costs and increasing production yield. In this thesis a method that allows testing of individual optical components within a complex optical integrated circuit is described. The method is based on diffractive grating couplers, which can be used to efficiently couple light from an optical fibre to a silicon waveguide. In this work gratings are fabricated by the introduction of lattice disorder, induced by ion implantation of germanium opposed to the typical surface relief structure typically used. The lattice damage alters the crystalline structure of silicon, hence causing a change in the refractive index. Coupling performance determined empirically, showed a 5.5dB loss between the fibre and planar waveguide modes, which is not dissimilar to the performance of typical uniform surface relief gratings currently used.
Gratings fabricated using this method can be erased via localised laser annealing after device testing is completed. Annealing is shown reduce the outcoupling efficiency of the gratings fabricated by ~21dB. Laser annealing was achieved by employing a continuous wave laser, operating at visible wavelengths thus reducing equipment costs compared with traditional annealing systems, which use a pulsed, deep ultra violet laser. The process developed retains CMOS compatibility which enables the design to be used in current microelectronics fabrication facilities.
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Published date: October 2014
Organisations:
University of Southampton, Optoelectronics Research Centre
Identifiers
Local EPrints ID: 371751
URI: http://eprints.soton.ac.uk/id/eprint/371751
PURE UUID: 90d965da-adc6-43c9-a1c6-711e8ec9609c
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Date deposited: 13 Nov 2014 13:19
Last modified: 14 Mar 2024 18:26
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Contributors
Author:
Robert Topley
Thesis advisor:
G.T. Reed
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