High-quality statistical test compression with narrow ATE interface
High-quality statistical test compression with narrow ATE interface
In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.
1369-1382
Tenentes, V.
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Kavousianos, X.
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September 2013
Tenentes, V.
1bff9ebc-9186-438b-850e-6c738994fa39
Kavousianos, X.
cd133613-8c16-46cf-a5be-91fd825e47cd
Tenentes, V. and Kavousianos, X.
(2013)
High-quality statistical test compression with narrow ATE interface.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32 (9), .
(doi:10.1109/TCAD.2013.2256394).
Abstract
In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.
Text
Tenentes_TCAD-2013.pdf
- Accepted Manuscript
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Published date: September 2013
Organisations:
Electronic & Software Systems
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Local EPrints ID: 377315
URI: http://eprints.soton.ac.uk/id/eprint/377315
PURE UUID: b247c968-8595-406f-8003-bd3728edaeed
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Date deposited: 11 Jun 2015 11:46
Last modified: 14 Mar 2024 20:00
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Author:
V. Tenentes
Author:
X. Kavousianos
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