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Resilient Routing Implementation in 2D Mesh NoC

Resilient Routing Implementation in 2D Mesh NoC
Resilient Routing Implementation in 2D Mesh NoC
With the rapid shrinking of technology and growing integration capacity, the probability of failures in Networks-on-Chip (NoCs) increases and thus, fault tolerance is essential. Moreover, the unpredictable locations of these failures may influence the regularity of the underlying topology, and a regular 2D mesh is likely to become irregular. Thus, for these failure-prone networks, a viable routing framework should comprise a topology-agnostic routing algorithm along with a cost-effective, scalable routing mechanism able to handle failures, irrespective of any particular failure patterns. Existing routing techniques designed to route irregular topologies efficiently lack flexibility (logic-based), scalability (table-based) or relaxed switch design (uLBDR-based). Designing an efficient routing implementation technique to address irregular topologies remains a pressing research problem. To address this, we present a fault resilient routing mechanism for irregular 2D meshes resulting from failures. To handle irregularities, it avoids using routing tables and employs a few fixed configuration bits per switch resulting in a scalable approach. Experiments demonstrate that the proposed approach is guaranteed to tolerate all locations of single and double-link failures and most multiple failures. Also, unlike uLBDR it is not restricted to any particular switching technique and does not replicate any extra messages. Along with fault tolerance, the proposed mechanism can achieve better network performance in fault-free cases. The proposed technique achieves graceful performance degradation during failure. Compared to uLBDR, our method has 14% less area requirements and 16% less overall power consumption.
0026-2714
Bishnoi, Rimpy
eb225b32-9ddb-4360-9b0b-d2e26a5e843e
Laxmi, Vijay
e79a9a3a-cd6b-45d6-8a03-9a5891453a95
Gaur, Manoj Singh
daa3f35d-eb48-4b0a-99e2-3703a88d54a2
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Bishnoi, Rimpy
eb225b32-9ddb-4360-9b0b-d2e26a5e843e
Laxmi, Vijay
e79a9a3a-cd6b-45d6-8a03-9a5891453a95
Gaur, Manoj Singh
daa3f35d-eb48-4b0a-99e2-3703a88d54a2
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Bishnoi, Rimpy, Laxmi, Vijay, Gaur, Manoj Singh and Zwolinski, Mark (2015) Resilient Routing Implementation in 2D Mesh NoC. Microelectronics Reliability. (doi:10.1016/j.microrel.2015.11.003).

Record type: Article

Abstract

With the rapid shrinking of technology and growing integration capacity, the probability of failures in Networks-on-Chip (NoCs) increases and thus, fault tolerance is essential. Moreover, the unpredictable locations of these failures may influence the regularity of the underlying topology, and a regular 2D mesh is likely to become irregular. Thus, for these failure-prone networks, a viable routing framework should comprise a topology-agnostic routing algorithm along with a cost-effective, scalable routing mechanism able to handle failures, irrespective of any particular failure patterns. Existing routing techniques designed to route irregular topologies efficiently lack flexibility (logic-based), scalability (table-based) or relaxed switch design (uLBDR-based). Designing an efficient routing implementation technique to address irregular topologies remains a pressing research problem. To address this, we present a fault resilient routing mechanism for irregular 2D meshes resulting from failures. To handle irregularities, it avoids using routing tables and employs a few fixed configuration bits per switch resulting in a scalable approach. Experiments demonstrate that the proposed approach is guaranteed to tolerate all locations of single and double-link failures and most multiple failures. Also, unlike uLBDR it is not restricted to any particular switching technique and does not replicate any extra messages. Along with fault tolerance, the proposed mechanism can achieve better network performance in fault-free cases. The proposed technique achieves graceful performance degradation during failure. Compared to uLBDR, our method has 14% less area requirements and 16% less overall power consumption.

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More information

Accepted/In Press date: 5 November 2015
e-pub ahead of print date: 14 November 2015
Organisations: EEE

Identifiers

Local EPrints ID: 383931
URI: http://eprints.soton.ac.uk/id/eprint/383931
ISSN: 0026-2714
PURE UUID: 206cfb98-2df3-4c8b-949e-08c8fbef1810
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

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Date deposited: 25 Nov 2015 10:31
Last modified: 08 Oct 2019 00:56

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Contributors

Author: Rimpy Bishnoi
Author: Vijay Laxmi
Author: Manoj Singh Gaur
Author: Mark Zwolinski ORCID iD

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