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BER plots for the paper of "A 1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder for MCMTC applications"

BER plots for the paper of "A 1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder for MCMTC applications"
BER plots for the paper of "A 1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder for MCMTC applications"
FPTD, LTE, Turbo code, FPGA
University of Southampton
Li, An
099fae06-fd69-4cab-933c-43a9b94ce1f1
Li, An
099fae06-fd69-4cab-933c-43a9b94ce1f1

Li, An (2016) BER plots for the paper of "A 1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder for MCMTC applications". University of Southampton doi:10.5258/SOTON/396816 [Dataset]

Record type: Dataset

Abstract

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Plots_FPGA.zip - Dataset
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More information

Published date: 2016
Related URLs:
Keywords: FPTD, LTE, Turbo code, FPGA
Organisations: Electronics & Computer Science
Projects:
Channel Decoder Architectures for Energy-Constrained Wireless Communication Systems: Holistic Approach
Funded by: UNSPECIFIED (EP/J015520/1)
12 October 2012 to 11 October 2015
Highly-Parallel Algorithms and Architectures for High-Throughput Wireless Receivers
Funded by: UNSPECIFIED (EP/L010550/1)
1 April 2014 to 31 March 2017
HARNet - (Harmonised Antennas, Radios, and Networks)
Funded by: UNSPECIFIED (TS/L009390/1)
1 October 2013 to 31 December 2015
Learn more about Electronics & Computer Science research

Identifiers

Local EPrints ID: 396816
URI: http://eprints.soton.ac.uk/id/eprint/396816
DOI: doi:10.5258/SOTON/396816
PURE UUID: 8ff8dccf-8c69-41ac-a13b-5d8388309fd4

Catalogue record

Date deposited: 09 Aug 2016 16:08
Last modified: 04 Nov 2023 14:57

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Contributors

Creator: An Li

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