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Thermally-aware composite run-time CPU power models

Thermally-aware composite run-time CPU power models
Thermally-aware composite run-time CPU power models
Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31 degrees C to 91 degrees C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5.
Walker, Matthew J.
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Diestelhorst, Stephan
5ac0a14f-5a42-4e09-a173-399b97170272
Hansson, Andreas
b535ff1d-9917-4816-b36f-59d1ad2bd137
Balsamo, Domenico
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Merrett, Geoff V.
89b3a696-41de-44c3-89aa-b0aa29f54020
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Walker, Matthew J.
77e58c74-1541-4ffc-9219-4c8c11248a2e
Diestelhorst, Stephan
5ac0a14f-5a42-4e09-a173-399b97170272
Hansson, Andreas
b535ff1d-9917-4816-b36f-59d1ad2bd137
Balsamo, Domenico
fa2dc20a-e3da-4d74-9070-9c61c6a471ba
Merrett, Geoff V.
89b3a696-41de-44c3-89aa-b0aa29f54020
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d

Walker, Matthew J., Diestelhorst, Stephan, Hansson, Andreas, Balsamo, Domenico, Merrett, Geoff V. and Al-Hashimi, Bashir M. (2016) Thermally-aware composite run-time CPU power models. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Bremen, Germany. 21 - 23 Sep 2016. 8 pp . (In Press)

Record type: Conference or Workshop Item (Paper)

Abstract

Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31 degrees C to 91 degrees C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5.

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More information

Accepted/In Press date: July 2016
Venue - Dates: International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Bremen, Germany, 2016-09-21 - 2016-09-23
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 398572
URI: http://eprints.soton.ac.uk/id/eprint/398572
PURE UUID: d2bd4167-5529-4b6e-8651-d8f9fd83d4e4
ORCID for Matthew J. Walker: ORCID iD orcid.org/0000-0001-6368-3644
ORCID for Geoff V. Merrett: ORCID iD orcid.org/0000-0003-4980-3894

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Date deposited: 27 Jul 2016 15:52
Last modified: 15 Mar 2024 03:23

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Contributors

Author: Matthew J. Walker ORCID iD
Author: Stephan Diestelhorst
Author: Andreas Hansson
Author: Domenico Balsamo
Author: Geoff V. Merrett ORCID iD
Author: Bashir M. Al-Hashimi

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