Thermally-aware composite run-time CPU power models
Walker, Matthew J., Diestelhorst, Stephan, Hansson, Andreas, Balsamo, Domenico, Merrett, Geoff V. and Al-Hashimi, Bashir M. (2016) Thermally-aware composite run-time CPU power models At International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Germany. 21 - 23 Sep 2016. 8 pp.
- Accepted Manuscript
Available under License Creative Commons Attribution.
Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31 degrees C to 91 degrees C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5.
|Item Type:||Conference or Workshop Item (Paper)|
|Venue - Dates:||International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Germany, 2016-09-21 - 2016-09-23
|Organisations:||Electronic & Software Systems|
|Date Deposited:||27 Jul 2016 15:52|
|Last Modified:||22 Feb 2017 04:01|
PRiME: Power-efficient, Reliable, Many-core Embedded systems
Funded by: EPSRC (EP/K034448/1)
Led by: Bashir M. Al-Hashimi
13 May 2013 to 12 May 2018
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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