Survey of ASIC implementations of LDPC decoders
Survey of ASIC implementations of LDPC decoders
This survey characterises the flexibility, throughput, area efficiency and energy efficiency of 62 different ASIC implementations of LDPC decoders. In general, the results show that increasing the number of supported parity check matrices by 10 times reduces each of the achievable throughput, area efficiency and energy efficiency by 10 times.
University of Southampton
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Maunder, Robert
(2016)
Survey of ASIC implementations of LDPC decoders.
University of Southampton
doi:10.5258/SOTON/399259
[Dataset]
Abstract
This survey characterises the flexibility, throughput, area efficiency and energy efficiency of 62 different ASIC implementations of LDPC decoders. In general, the results show that increasing the number of supported parity check matrices by 10 times reduces each of the achievable throughput, area efficiency and energy efficiency by 10 times.
Spreadsheet
LDPCdecoderASICsurvey.xlsx
- Dataset
Available under License Data: Open Database License (ODbL) (Attribution-Share Alike).
Available under License Data: Open Database License (ODbL) (Attribution-Share Alike).
More information
Published date: 2016
Organisations:
Southampton Wireless Group
Projects:
Highly-Parallel Algorithms and Architectures for High-Throughput Wireless Receivers
Funded by: UNSPECIFIED (EP/L010550/1)
1 April 2014 to 31 March 2017
Identifiers
Local EPrints ID: 399259
URI: http://eprints.soton.ac.uk/id/eprint/399259
PURE UUID: 61c65c7f-5544-490e-8001-db9b8b93d93b
Catalogue record
Date deposited: 09 Aug 2016 20:33
Last modified: 05 Nov 2023 02:43
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Contributors
Creator:
Robert Maunder
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